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high performance, 145 mhz fastfet ? op amps ad8065/ad8066 rev. g information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2006 analog devices, inc. all rights reserved. features fet input amplifier 1 pa input bias current low cost high speed: 145 mhz, ?3 db bandwidth (g = +1) 180 v/s slew rate (g = +2) low noise 7 nv/hz (f = 10 khz) 0.6 fa/hz (f = 10 khz) wide supply voltage range: 5 v to 24 v single-supply and rail-to-rail output low offset voltage 1.5 mv maximum high common-mode rejection ratio: ?100 db excellent distortion specifications sfdr ?88 dbc @ 1 mhz low power: 6.4 ma/amplifier typical supply current no phase reversal small packaging: soic-8, sot-23-5, and msop-8 applications instrumentation photodiode preamps filters a/d drivers level shifting buffering connection diagrams 1 2 3 5 4 1 4 3 5 27 8 6 8 7 6 5 1 2 3 4 v out v out1 v out2 v out ?v s ?v s ?v s +in +v s +v s +v s ?in ?in1 +in1 ?in2 +in2 nc ?in +in nc nc top view (not to scale) top view (not to scale) top view (not to scale) ad8065 ad8066 ad8065 02916-e-001 figure 1. general description the ad8065/ad8066 1 fastfet amplifiers are voltage feedback amplifiers with fet inputs offering high performance and ease of use. the ad8065 is a single amplifier, and the ad8066 is a dual amplifier. these amplifiers are developed in the analog devices, inc. proprietary xfcb process and allow exceptionally low noise operation (7.0 nv/hz and 0.6 fa/ hz) as well as very high input impedance. with a wide supply voltage range from 5 v to 24 v, the ability to operate on single supplies, and a bandwidth of 145 mhz, the ad8065/ad8066 are designed to work in a variety of applications. for added versatility, the amplifiers also contain rail-to-rail outputs. despite the low cost, the amplifiers provide excellent overall performance. the differential gain and phase errors of 0.02% and 0.02, respectively, along with 0.1 db flatness out to 7 mhz, make these amplifiers ideal for video applications. additionally, they offer a high slew rate of 180 v/s, excellent distortion (sfdr of ?88 dbc @ 1 mhz), extremely high common-mode rejection of ?100 db, and a low input offset voltage of 1.5 mv maximum under warmed up conditions. the ad8065/ ad8066 operate using only a 6.4 ma/amplifier typical supply current and are capable of delivering up to 30 ma of load current. the ad8065/ad8066 are high performance, high speed, fet input amplifiers available in small packages: soic-8, msop-8, and sot-23-5. they are rated to work over the industrial temperature range of ?40c to +85c. ?6 ?3 0 3 6 9 12 15 18 21 24 gain (db) frequency (mhz) 1 0.1 10 100 1000 02916-e-002 g = +10 v o = 200mv p-p g = +5 g = +2 g = +1 figure 2. small signal frequency response 1 protected by u. s. patent no. 6,262,633.
ad8065/ad8066 rev. g | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 maximum power dissipation ..................................................... 7 output short circuit .................................................................... 7 typical performance characteristics ............................................. 8 test circ u its ................................................................................. 15 theory of operation ...................................................................... 18 closed-loop frequency response ........................................... 18 noninverting closed-loop frequency response .................. 18 inverting closed-loop frequency response ......................... 18 wideband operation ................................................................. 19 input protection ......................................................................... 19 thermal considerations ............................................................ 20 input and output overload behavior ..................................... 20 layout, grounding, and bypassing considerations .................. 21 power supply bypassing ............................................................ 21 grounding ................................................................................... 21 leakage currents ........................................................................ 22 input capacitance ...................................................................... 22 output capacitance ................................................................... 22 input-to-output coupling ........................................................ 23 wideband photodiode preamp ................................................ 23 high speed jfet input instrumentation amplifier .............. 24 video buffer ................................................................................ 24 outline dimensions ....................................................................... 25 ordering guide .......................................................................... 26 revision history 1/06rev. f to rev. g changes to ordering guide .......................................................... 26 12/05rev. e to rev. f updated format..................................................................universal changes to features.......................................................................... 1 changes to general description .................................................... 1 changes to figure 22 through figure 27 ..................................... 11 updated outline dimensions ....................................................... 25 changes to ordering guide .......................................................... 26 2/04data sheet changed from rev. d to rev. e. updated format................................................................ universal updated figure 56 ......................................................................... 21 updated outline dimensions ...................................................... 25 updated ordering guide.............................................................. 26 11/03data sheet changed from rev. c to rev. d. changes to features......................................................................... 1 changes to connection diagrams ................................................ 1 updated ordering guide................................................................ 5 updated outline dimensions ...................................................... 22 4/03data sheet changed from rev. b to rev. c. added soic-8 (r) for the ad8065............................................... 4 2/03data sheet changed from rev. a to rev. b. changes to absolute maximum ratings...................................... 4 changes to test circuit 10 ........................................................... 14 changes to test circuit 11 ........................................................... 15 changes to noninverting closed-loop frequency response 16 changes to inverting closed-loop frequency response ....... 16 updated figure 6 .......................................................................... 18 changes to figure 7....................................................................... 19 changes to figure 10..................................................................... 21 changes to figure 11..................................................................... 22 changes to high speed jfet instrumentation amplifier....... 22 changes to video buffer............................................................... 22 8/02data sheet changed from rev. 0 to rev. a. added ad8066 ..................................................................universal added soic-8 (r) and msop-8 (rm) ........................................ 1 edits to general description ......................................................... 1 edits to specifications ..................................................................... 2 new figure 2 .................................................................................... 5 changes to ordering guide ........................................................... 5 edits to tpcs 18, 25, and 28 .......................................................... 8 new tpc 36 ................................................................................... 11 added test circuits 10 and 11..................................................... 14 msop (rm-8) added.................................................................... 23
ad8065/ad8066 rev. g | page 3 of 28 specifications @ t a = 25c, v s = 5 v, r l = 1 k, unless otherwise noted. table 1. parameter conditions min typ max unit dynamic performance ?3 db bandwidth g = +1, v o = 0.2 v p-p (ad8065) 100 145 mhz g = +1, v o = 0.2 v p-p (ad8066) 100 120 mhz g = +2, v o = 0.2 v p-p 50 mhz g = +2, v o = 2 v p-p 42 mhz bandwidth for 0.1 db flatness g = +2, v o = 0.2 v p-p 7 mhz input overdrive recovery time g = +1, ?5.5 v to +5.5 v 175 ns output recovery time g = ?1, ?5.5 v to +5.5 v 170 ns slew rate g = +2, v o = 4 v step 130 180 v/s settling time to 0.1% g = +2, v o = 2 v step 55 ns g = +2, v o = 8 v step 205 ns noise/harmonic performance sfdr f c = 1 mhz, g = +2, v o = 2 v p-p ?88 dbc f c = 5 mhz, g = +2, v o = 2 v p-p ?67 dbc f c = 1 mhz, g = +2, v o = 8 v p-p ?73 dbc third-order intercept f c = 10 mhz, r l = 100 24 dbm input voltage noise f = 10 khz 7 nv/hz input current noise f = 10 khz 0.6 fa/hz differential gain error ntsc, g = +2, r l = 150 0.02 % differential phase error ntsc, g = +2, r l = 150 0.02 degrees dc performance input offset voltage v cm = 0 v, soic package 0.4 1.5 mv input offset voltage drift 1 17 v/c input bias current soic package 2 6 pa t min to t max 25 pa input offset current 1 10 pa t min to t max 1 pa open-loop gain v o = 3 v, r l = 1 k 100 113 db input characteristics common-mode input impedance 1000 || 2.1 g || pf differential input impedance 1000 || 4.5 g || pf input common-mode voltage range fet input range ?5 to +1.7 ?5.0 to +2.4 v usable range see the theory of operation section ?5.0 to +5.0 v common-mode rejection ratio v cm = ?1 v to +1 v ?85 ?100 db v cm = ?1 v to +1 v (sot-23) ?82 ?91 db output characteristics output voltage swing r l = 1 k ?4.88 to +4.90 ?4.94 to +4.95 v r l = 150 ?4.8 to +4.7 v output current v o = 9 v p-p, sfdr ?60 dbc, f = 500 khz 35 ma short-circuit current 90 ma capacitive load drive 30% overshoot g = +1 20 pf power supply operating range 5 24 v quiescent current per amplifier 6.4 7.2 ma power supply rejection ratio psrr ?85 ?100 db
ad8065/ad8066 rev. g | page 4 of 28 @ t a = 25c, v s = 12 v, r l = 1 k, unless otherwise noted. table 2. parameter conditions min typ max unit dynamic performance ?3 db bandwidth g = +1, v o = 0.2 v p-p (ad8065) 100 145 mhz g = +1, v o = 0.2 v p-p (ad8066) 100 115 mhz g = +2, v o = 0.2 v p-p 50 mhz g = +2, v o = 2 v p-p 40 mhz bandwidth for 0.1 db flatness g = +2, v o = 0.2 v p-p 7 mhz input overdrive recovery g = +1, ?12.5 v to +12.5 v 175 ns output overdrive recovery g = ?1, ?12.5 v to +12.5 v 170 ns slew rate g = +2, v o = 4 v step 130 180 v/s settling time to 0.1% g = +2, v o = 2 v step 55 ns g = +2, v o = 10 v step 250 ns noise/harmonic performance sfdr f c = 1 mhz, g = +2, v o = 2 v p-p ?100 dbc f c = 5 mhz, g = +2, v o = 2 v p-p ?67 dbc f c = 1 mhz, g = +2, v o = 10 v p-p ?85 dbc third-order intercept f c = 10 mhz, r l = 100 24 dbm input voltage noise f = 10 khz 7 nv/hz input current noise f = 10 khz 1 fa/hz differential gain error ntsc, g = +2, r l = 150 0.04 % differential phase error ntsc, g = +2, r l = 150 0.03 degrees dc performance input offset voltage v cm = 0 v, soic package 0.4 1.5 mv input offset voltage drift 1 17 v/c input bias current soic package 3 7 pa t min to t max 25 pa input offset current 2 10 pa t min to t max 2 pa open-loop gain v o = 10 v, r l = 1 k 103 114 db input characteristics common-mode input impedance 1000 || 2.1 g || pf differential input impedance 1000 || 4.5 g || pf input common-mode voltage range fet input range ?12 to +8.5 ?12.0 to +9.5 v usable range see the theory of operation section ?12.0 to +12.0 v common-mode rejection ratio v cm = ?1 v to +1 v ?85 ?100 db v cm = ?1 v to +1 v (sot-23) ?82 ?91 db output characteristics output voltage swing r l = 1 k ?11.8 to +11.8 ?11.9 to +11.9 v r l = 350 ?11.25 to +11.5 v output current v o = 22 v p-p, sfdr ?60 dbc, f = 500 khz 30 ma short-circuit current 120 ma capacitive load drive 30% overshoot g = +1 25 pf power supply operating range 5 24 v quiescent current per amplifier 6.6 7.4 ma power supply rejection ratio psrr ?84 ?93 db
ad8065/ad8066 rev. g | page 5 of 28 @ t a = 25c, v s = 5 v, r l = 1 k, unless otherwise noted. table 3. parameter conditions min typ max unit dynamic performance ?3 db bandwidth g = +1, v o = 0.2 v p-p (ad8065) 125 155 mhz g = +1, v o = 0.2 v p-p (ad8066) 110 130 mhz g = +2, v o = 0.2 v p-p 50 mhz g = +2, v o = 2 v p-p 43 mhz bandwidth for 0.1 db flatness g = +2, v o = 0.2 v p-p 6 mhz input overdrive recovery time g = +1, ?0.5 v to +5.5 v 175 ns output recovery time g = ?1, ?0.5 v to +5.5 v 170 ns slew rate g = +2, v o = 2 v step 105 160 v/s settling time to 0.1% g = +2, v o = 2 v step 60 ns noise/harmonic performance sfdr f c = 1 mhz, g = +2, v o = 2 v p-p ?65 dbc f c = 5 mhz, g = +2, v o = 2 v p-p ?50 dbc third-order intercept f c = 10 mhz, r l = 100 22 dbm input voltage noise f = 10 khz 7 nv/hz input current noise f = 10 khz 0.6 fa/hz differential gain error ntsc, g = +2, r l = 150 0.13 % differential phase error ntsc, g = +2, r l = 150 0.16 degrees dc performance input offset voltage v cm = 1.0 v, soic package 0.4 1.5 mv input offset voltage drift 1 17 v/oc input bias current soic package 1 5 pa t min to t max 25 pa input offset current 1 5 pa t min to t max 1 pa open-loop gain v o = 1 v to 4 v (ad8065) 100 113 db v o = 1 v to 4 v (ad8066) 90 103 db input characteristics common-mode input impedance 1000 || 2.1 g || pf differential input impedance 1000 || 4.5 g || pf input common-mode voltage range fet input range 0 to 1.7 0 to 2.4 v usable range see the theory of operation section 0 to 5.0 v common-mode rejection ratio v cm = 0.5 v to 1.5 v ?74 ?100 db v cm = 1 v to 2 v (sot-23) ?78 ?91 db output characteristics output voltage swing r l = 1 k 0.1 to 4.85 0.03 to 4.95 v r l = 150 0.07 to 4.83 v output current v o = 4 v p-p, sfdr ?60 dbc, f = 500 khz 35 ma short-circuit current 75 ma capacitive load drive 30% overshoot g = +1 5 pf power supply operating range 5 24 v quiescent current per amplifier 5.8 6.4 7.0 ma power supply rejection ratio psrr ?78 ?100 db
ad8065/ad8066 rev. g | page 6 of 28 absolute maximum ratings table 4. parameter rating supply voltage 26.4 v power dissipation see figure 3 common-mode input voltage v ee ? 0.5 v to v cc + 0.5 v differential input voltage 1.8 v storage temperature range ?65c to +125c operating temperature range ?40c to +85c lead temperature (soldering, 10 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd pr ecautions are recommended to avoid performance degradation or loss of functionality.
ad8065/ad8066 rev. g | page 7 of 28 maximum power dissipation the maximum safe power dissipation in the ad8065/ad8066 packages is limited by the associated rise in junction temperature (t j ) on the die. the plastic encapsulating the die locally reaches the junction temperature. at approximately 150c, which is the glass transition temperature, the plastic changes its properties. even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ad8065/ad8066. exceeding a junction temperature of 175c for an extended time can result in changes in the silicon devices, potentially causing failure. the still air thermal properties of the package and pcb ( ja ), ambient temperature (t a ), and total power dissipated in the package (p d ) determine the junction temperature of the die. the junction temperature can be calculated by t j = t a + ( p d ja ) the power dissipated in the package (p d ) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. the quiescent power is the voltage between the supply pins (v s ) times the quiescent current (i s ). assuming the load (r l ) is referenced to midsupply, then the total drive power is v s /2 i out , some of which is dissipated in the package and some in the load (v out i out ). the difference between the total drive power and the load power is the drive power dissipated in the package. ( ) powerload powerdrivetotal power quiescent p d ? + = () l out l out s ss d r v r vv ivp 2 2 ? ? ? ? ? ? ? += rms output voltages should be considered. if r l is referenced to v s ?, as in single-supply operation, then the total drive power is v s i out . if the rms signal levels are indeterminate, then consider the worst case, when v out = v s /4 for r l to midsupply. () () l s ss d r v ivp 2 4/ += in single-supply operation with r l referenced to v s ?, worst case is v out = v s /2. maximum power dissipation (w) 0 0.5 1.0 1.5 2.0 20 0 ?40 ?20 ?60 40 60 80 100 ambient temperature (c) 02916-e-003 msop-8 soic-8 sot-23-5 figure 3. maximum power dissipation vs. temperature for a 4-layer board airflow increases heat dissipation, effectively reducing ja . also, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduce the ja . care must be taken to minimize parasitic capacitances at the input leads of high speed op amps as discussed in the layout, grounding, and bypassing considerations section. figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the soic (125c/w), sot-23 (180c/w), and msop (150c/w) packages on a jedec standard 4-layer board. ja values are approximations. output short circuit shorting the output to ground or drawing excessive current for the ad8065/ad8066 will likely cause catastrophic failure.
ad8065/ad8066 rev. g | page 8 of 28 typical performance characteristics default c onditions: 5 v, c l = 5 pf, r l = 1 k, v out = 2 v p-p, t emperature = 25c. ?6 ?3 0 3 6 9 12 15 18 21 24 gain (db) frequency (mhz) 1 0.1 10 100 1000 02916-e-004 g = +10 v o = 200mv p-p g = +5 g = +2 g = +1 figure 4. small signal frequency response for various gains ?6 ?4 ?2 0 2 4 6 gain (db) frequency (mhz) 1 0.1 10 100 1000 02916-e-005 v o = 200mv p-p g = +1 v s = +5v v s = 12v v s = 5v figure 5. small signal frequency response for various supplies (see figure 42 ) ?5 ?4 ?3 ?2 ?1 0 1 2 gain (db) frequency (mhz) 1 0.1 10 100 1000 02916-e-006 v o = 2v p-p g = +1 v s = 12v v s = 5v figure 6. large signal frequency response for various supplies (see figure 42 ) 5.9 6.0 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 gain (db) frequency (mhz) 0.1 10 1 100 02916-e-007 r l = 150 g = +2 v out = 0.2v p-p v out = 0.7v p-p v out = 1.4v p-p figure 7. 0.1 db flatness frequency response (see figure 43 ) 3 4 5 6 7 8 9 gain (db) frequency (mhz) 1 0.1 10 100 1000 02916-e-008 v o = 200mv p-p g = +2 v s = 12v v s = 5v v s = +5v figure 8. small signal frequency response for various supplies (see figure 43 ) 0 1 2 3 4 5 gain (db) 6 7 8 frequency (mhz) 1 0.1 10 100 1000 02916-e-009 g = +2 v s = 12v v s = 5v v s = +5v figure 9. large signal frequency response for various supplies (see figure 43 )
ad8065/ad8066 rev. g | page 9 of 28 ?9 ?6 ?3 0 3 6 9 gain (db) frequency (mhz) 1 0.1 10 100 1000 02916-e-010 g = +1 c l = 25pf c l = 25pf r snub = 20 c l = 20pf c l = 5pf v o = 200mv p-p figure 10. small signal frequency response for various c load (see figure 42 ) ?8 ?6 ?4 ?2 0 2 gain (db) 4 6 8 frequency (mhz) 1 0.1 10 100 1000 02916-e-011 g = +2 v out = 0.2v p-p v out = 2v p-p v out = 4v p-p figure 11. frequency response for various output amplitudes (see figure 43 ) ?4 ?2 0 2 4 6 8 10 12 14 gain (db) frequency (mhz) 1 0.1 10 100 1000 02916-e-012 g = +2 r f = r g = 1k , r s = 500 r f = r g = 500 , r s = 250 r f = r g = 500 , r s = 250 , c f = 2.2pf r f = r g = 1k , r s = 500 , c f = 3.3pf v o = 200mv p-p figure 12. small signal frequency response for various r f /c f (see figure 43 ) ?8 ?6 ?4 ?2 0 2 gain (db) 4 6 8 frequency (mhz) 1 0.1 10 100 1000 02916-e-013 c l = 25pf c l = 55pf c l = 5pf v o = 200mv p-p g = +2 figure 13. small signal frequency response for various c load (see figure 43 ) 0 1 2 3 4 5 gain (db) 6 7 8 frequency (mhz) 1 0.1 10 100 1000 02916-e-014 r l = 100 r l = 1k v o = 200mv p-p g = +2 figure 14. small signal frequency response for various r load (see figure 43 ) ?180 ?120 ?60 0 60 120 phase (degrees) ?20 0 20 40 60 80 open-loop gain (db) 0.01 0.1 1 10 100 1000 frequency (mhz) 02916-e-015 phase gain figure 15. open-loop response
ad8065/ad8066 rev. g | page 10 of 28 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 distortion (dbc) frequency (mhz) 0.1 10 1 100 02916-e-016 hd3 r l = 150 hd2 r l = 150 hd3 r l = 1k hd2 r l = 1k g = +2 figure 16. harmonic distortion vs. frequency for various loads (see figure 43 ) ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 distortion (dbc) 01234 6 10 5 789 12 11 1413 15 output amplitude (v p-p) 02916-e-017 hd3 r l = 150 hd2 r l = 150 hd3 r l = 300 hd2 r l = 300 g = +2 v s = 12v f = 1mhz figure 17. harmonic distortion vs. amplitude for various loads v s = 12 v (see figure 43 ) 15 20 25 30 35 40 45 50 intercept point (dbm) frequency (mhz) 11 0 02916-e-018 v s = 12v r l = 100 v s = 5v v s = +5v figure 18. third-order intercept vs. frequency and supply voltage ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 distortion (dbc) frequency (mhz) 0.1 10 1 100 02916-e-019 hd2 g = +2 hd3 g = +2 hd2 g = +1 hd3 g = +1 figure 19. harmonic distortion vs. frequency for various gains (see figure 42 and figure 43 ) ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 distortion (dbc) frequency (mhz) 0.1 1.0 10.0 02916-e-020 hd2 v o = 20v p-p hd3 v o = 20v p-p hd2 v o = 10v p-p hd3 v o = 10v p-p hd2 v o = 2v p-p hd3 v o = 2v p-p v s = 12v g = +2 figure 20. harmonic distortion vs. frequency for various amplitudes (see figure 43 ) noise (nv/ hz) 1 10 100 100k 10k 100 1k 10 1m 10m 100m 1g frequency (hz) 02916-e-021 figure 21. voltage noise
ad8065/ad8066 rev. g | page 11 of 28 02916-022 g = +1 50mv/div 25ns/div figure 22. small signal transient response 5 v supply (see figure 42 ) 02916-023 g = +1 2v/div 50ns/div v s = 12v v out = 2v p-p v out = 4v p-p v out = 10v p-p figure 23. large signal transient response (see figure 42 ) 02916-024 2.0v/div 100ns/div g = ?1 v s = 5v figure 24. output ov erdrive recovery (see figure 44 ) 02916-025 g = +1 50mv/div 25ns/div c l = 5pf c l = 20pf figure 25. small signal transient response 5 v (see figure 42 ) 02916-026 5s g = +2 2v/div 50ns/div v s = 12v v out = 10v p-p v out = 2v p-p figure 26. large signal transient response (see figure 43 ) 02916-027 2.0v/div 100ns/div g = +1 v s = 5v figure 27. input overdrive recovery (see figure 42 )
ad8065/ad8066 rev. g | page 12 of 28 02916-e-028 t = 0 64 s/div 2mv/div +0.1% ?0.1% v in = 140mv/div v out ? 2v in figure 28. long-term settling time (see figure 49 ) ?30 ?25 ?20 ?15 ?10 ?5 0 input bias current (pa) 45 55 25 35 65 75 85 temperature (c) 02916-e-029 ?i b +i b figure 29. input bias current vs. temperature ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 offset voltage (mv) ?14 ?10 ?12 ?8?6?4 0 8 ?2 2 4 6 10 12 14 common-mode voltage (v) 02916-e-030 v s = 12v v s = 5v v s = +5v figure 30. input offset voltage vs. common-mode voltage 02916-e-031 +0.1% 2mv/div 10ns/div ?0.1% t = 0 v out ? 2v in v in = 500mv/div figure 31. 0.1% short- term settling time (see figure 49 ) 02916-e-032 0 i b ( a) 36 30 24 18 12 6 ?5 ?15 ?25 ?30 0 i b (pa) ?12 8 ?2 ?10 0 ?8 2 ?6 4 ?4 6 common-mode voltage (v) 10 12 42 ?i b +i b ?i b +i b fet input stage bjt input stage ?20 ?10 5 10 figure 32. input bias current vs. common-mode voltage range (see the input and output overload behavior section) 02916-e-033 input offset voltage (mv) 35 15 0 ?2.0 2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 30 20 10 5 40 25 n = 299 sd = 0.388 mean = ?0.069 figure 33. input offset voltage
ad8065/ad8066 rev. g | page 13 of 28 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 cmrr (db) frequency (mhz) 0.1 10 1 100 02916-e-034 v s = 12v v s = 5v figure 34. cmrr vs. frequency (see figure 46 ) 0 0.05 0.10 0.15 0.20 0.25 0.30 output saturation voltage (v) i load (ma) 10 02 0 3 0 02916-e-035 v cc ? v oh v ol ? v ee 4 0 figure 35. output saturation voltage vs. output load current ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 psrr (db) 0.01 0.1 1 10 100 1000 frequency (mhz) 02916-e-036 ?psrr +psrr figure 36. psrr vs. frequency (see figure 48 and figure 50 ) 0 0.01 0.1 1 10 100 output impedance ( ) 10k 100k 100 1k 1m 10m 100m frequency (hz) 02916-e-037 g = +2 g = +1 figure 37. output impedance vs. frequency (see figure 45 and figure 47 ) 30 40 50 60 70 80 output saturation voltage (mv) 45 55 25 35 65 75 85 temperature (c) 02916-e-038 v cc ? v oh v ol ? v ee figure 38. output saturation voltage vs. temperature ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 crosstalk (db) frequency (mhz) 0.1 10 1 100 02916-e-039 v in = 2v p-p g = +1 b to a a to b figure 39. crosstalk vs. frequency (see figure 51 )
ad8065/ad8066 rev. g | page 14 of 28 6.25 6.30 6.35 6.40 6.45 6.50 6.55 6.60 supply current (ma) 020 ?40 ?20 40 60 80 temperature (c) 02916-e-040 v s = 12v v s = +5v v s = 5v figure 40. quiescent supply current vs. temperature for various supply voltages 80 85 90 95 100 105 110 115 120 125 open-loop gain (db) i load (ma) 10 02 0 3 0 02916-e-041 4 0 v s = 12v v s = +5v v s = 5v figure 41. open-loop gain vs. load current for various supply voltages
ad8065/ad8066 rev. g | page 15 of 28 test circuits soic-8 pinout ad8065 +v cc v in ?v ee 4.7 f 0.1 f 24.9 r snub 0.1 f 4.7 f c load fet probe 49.9 1k 02916-e-042 figure 42. g = +1 02916-e-043 ad8065 +v cc v in ?v ee 4.7 f 0.1 f 2.2pf r snub 0.1 f 4.7 f 49.9 499 499 249 c load fet probe 1k figure 43. g = +2 v in 49.9 ad8065 +v cc ?v ee 4.7 f 0.1 f 2.2pf 0.1 f 4.7 f 499 499 249 fet probe 1k 02916-e-044 figure 44. g = ?1 ad8065 +v cc ?v ee 4.7 f 0.1 f 24.9 0.1 f 4.7 f network analyzer s22 02916-e-045 figure 45. output impedance g = +1
ad8065/ad8066 rev. g | page 16 of 28 v in 49.9 ad8065 +v cc ?v ee 4.7 f 0.1 f 0.1 f 4.7 f 499 499 fet probe 1k 499 499 02916-e-046 figure 46. cmrr ad8065 +v cc ?v ee 0.1 f 4.7 f 499 499 249 network analyzer s22 4.7 f 0.1 f 02916-e-047 figure 47. output impedance g = +2 ad8065 ?v ee 24.9 0.1 f 4.7 f +v cc fet probe 1k v in 1v p-p 49.9 02916-e-048 figure 48. positive psrr ad8065 +v cc v in ?v ee 4.7 f 0.1 f 2.2pf 976 0.1 f 4.7 f 499 499 249 to scope 49.9 49.9 02916-e-049 figure 49. settling time
ad8065/ad8066 rev. g | page 17 of 28 ad8065 +v cc ?v ee 4.7 f 0.1 f fet probe 49.9 24.9 v in 1v p-p 1k 02916-e-050 figure 50. negative psrr 24.9 49.9 24.9 1k 0.1 f 4.7 f v in +5v ?5v 1k drive side receive side ad8066 ad8066 0.1 f 4.7 f fet probe 02916-e-051 figure 51. crosstalkad8066 249 0.1 f v in 1.5v 1.5v 1.5v 4.7 f 499 499 5v 49.9 2.2pf 1k fet probe ad8065 02916-e-052 figure 52. single supply
ad8065/ad8066 rev. g | page 18 of 28 theory of operation the ad8065/ad8066 are voltage feedback operational amplifiers that combine a laser-trimmed jfet input stage with the analog devices extra fast complementary bipolar (xfcb) process, resulting in an outstanding combination of precision and speed. the supply voltage range is from 5 v to 24 v. the amplifiers feature a patented rail-to-rail output stage capable of driving within 0.5 v of either power supply while sourcing or sinking up to 30 ma. also featured is a single-supply input stage that handles common-mode signals from below the negative supply to within 3 v of the positive rail. operation beyond the jfet input range is possible because of an auxiliary bipolar input stage that functions with input voltages up to the positive supply. the amplifiers operate as if they have a rail-to-rail input and exhibit no phase reversal behavior for common-mode voltages within the power supply. with voltage noise of 7 nv/hz and ?88 dbc distortion for 1 mhz, 2 v p-p signals, the ad8065/ad8066 are a great choice for high resolution data acquisition systems. their low noise, sub-pa input current, precision offset, and high speed make them superb preamps for fast photodiode applications. the speed and output drive capability of the ad8065/ad8066 also make them useful in video applications. closed-loop frequency response the ad8065/ad8066 are classic voltage feedback amplifiers with an open-loop frequency response that can be approx- imated as the integrator response shown in figure 53 . basic closed-loop frequency response for inverting and noninverting configurations can be derived from the schematics shown. noninverting closed-loop frequency response solving for the transfer function ( ) () g crossover g f f g crossover i o rfsrr rrf v v ++ + = 2 2 where f crossover is the frequency where the amplifiers open-loop gain equals 0 db at dc g g f i o r rr v v + = closed-loop ?3 db frequency g f g crossover 3db rr r ff + = ? inverting closed-loop frequency response () g crossover g f f crossover i o rfrrs rf v v ++ ? = 2 2 at dc g f i o r r v v ?= closed-loop ?3 db frequency gf g crossover db rr r ff + = ? 3 r f a v o r g v i v e freuenc (mhz) 80 60 0.01 100 open-loop gain (a) (db) 0.1 10 1 40 20 0 f crossover = 65mhz a = (2 figure 53. open-loop gain vs. frequency and basic connections
ad8065/ad8066 rev. g | page 19 of 28 the closed-loop bandwidth is inversely proportional to the noise gain of the op amp circuit, (r f + r g )/r g . this simple model is accurate for noise gains above 2. the actual bandwidth of circuits with noise gains at or below 2 are higher than those predicted with this model due to the influence of other poles in the frequency response of the real op amp. v o r f a r g v i i b ? r s i b + +v os ? 02916-e-054 figure 54. voltage feedback amplifier dc errors figure 54 shows a voltage feedback amplifiers dc errors. for both inverting and noninverting configurations () ? ? ? ? ? ? + +? ? ? ? ? ? ? + = ? + g f g os f b g f g s b o r rr vri r rr rierrorv the voltage error due to i b+ and i bC is minimized if r s = r f || r g (though with the ad8065 input currents at less than 20 pa over temperature, this is likely not a concern). to include common- mode and power supply rejection effects, total v os can be modeled cmr v psr v vv cm s nom osos ? ++= nom os v is the offset voltage specified at nominal conditions, v s is the change in power supply from nominal conditions, psr is the power supply rejection, v cm is the change in common-mode voltage from nominal conditions, and cmr is the common-mode rejection. wideband operation figure 42 through figure 44 show the circuits used for wideband characterization for gains of +1, +2, and ?1. source impedance at the summing junction (r f || r g ) will form a pole in the amplifiers loop response with the amplifiers input capacitance of 6.6 pf. this can cause peaking and ringing if the time constant formed is too low. feedback resistances of 300 to 1 k are recommended, since they will not unduly load down the amplifier and the time constant formed will not be too low. peaking in the frequency response can be compensated for with a small capacitor (c f ) in parallel with the feedback resistor, as illustrated in figure 12 . this shows the effect of different feedback capacitances on the peaking and bandwidth for a noninverting g = +2 amplifier. for the best settling times and the best distortion, the impedances at the ad8065/ad8066 input terminals should be matched. this minimizes nonlinear common-mode capacitive effects that can degrade ac performance. actual distortion performance depends on a number of variables: ? the closed-loop gain of the application ? whether it is inverting or noninverting ? amplifier loading ? signal frequency and amplitude ? board layout also see figure 16 to figure 20 . the lowest distortion is obtained with the ad8065 used in low gain inverting appli- cations, since this eliminates common-mode effects. higher closed-loop gains result in worse distortion performance. input protection the inputs of the ad8065/ad8066 are protected with back-to- back diodes between the input terminals as well as esd diodes to either power supply. this results in an input stage with picoamps of input current that can withstand up to 1500 v esd events (human body model) with no degradation. excessive power dissipation through the protection devices destroys or degrades the performance of the amplifier. differ- ential voltages greater than 0.7 v result in an input current of approximately (|v + ? v ? | 0.7 v)/r i , where r i is the resistance in series with the inputs. for input voltages beyond the positive supply, the input current is approximately (v i ? v cc ? 0.7)/r i . beyond the negative supply, the input current is about (v i ? v ee + 0.7)/r i . if the inputs of the amplifier are to be subjected to sustained differential voltages greater than 0.7 v, or to input voltages beyond the amplifier power supply, input current should be limited to 30 ma by an appropriately sized input resistor (r i ), as shown in figure 55 . r i v i v o ad8065 r i > (| v + ?v ? | ? 0.7v) 30ma for large | v + ?v ? | r i > (v i ?v ee ? 0.7v) 30ma r i > (v i ?v ee + 0.7v) 30ma for v i beyond supply voltages 02916-e-055 figure 55. current-limiting resistor
ad8065/ad8066 rev. g | page 20 of 28 thermal considerations with 24 v power supplies and 6.5 ma quiescent current, the ad8065 dissipates 156 mw with no load. the ad8066 dissipates 312 mw. this can lead to noticeable thermal effects, especially in the small sot-23-5 (thermal resistance of 160c/w). v os temperature drift is trimmed to guarantee a maximum drift of 17 v/c, so it can change up to 0.425 mv due to warm-up effects for an ad8065/ad8066 in a sot-23-5 package on 24 v. i b increases by a factor of 1.7 for every 10c rise in temperature. i b is close to five times higher at 24 v supplies as opposed to a single 5 v supply. heavy loads increase power dissipation and raise the chip junction temperature as described in the maximum power dissipation section. care should be taken to not exceed the rated power dissipation of the package. input and output overload behavior the ad8065/ad8066 have internal circuitry to guard against phase reversal due to overdriving the input stage. a simplified schematic of the input stage, including the input-protection diodes and antiphase reversal circuitry, is shown in figure 56 . the circuit is arranged such that when the input common- mode voltage exceeds a certain threshold, the input jfet pairs bias current turns off, and the bias current of an auxiliary npn pair turns on, taking over control of the amplifier. when the input common-mode voltage returns to a viable operating value, the fet stage turns back on, the npn stage turns off, and normal operation resumes. the npn pair can sustain operation with the input voltage up to the positive supply, so this is a pseudo rail-to-rail input stage. for operation beyond the fet stages common-mode limit, the amplifiers v os changes to the npn pairs offset (mean of 160 v, standard deviation of 820 v), and i b increases to the npn pairs base current up to 45 a (see figure 32 ). switchback, or recovery time, is about 100 ns, see figure 27 . the output transistors of the rail-to-rail output stage have circuitry to limit the extent of their saturation when the output is overdriven. this helps output recovery time. output recovery from a 0.5 v output overdrive on a 5 v supply is shown in figure 24 . v threshold vbias s v p to rest of amp v cc s v n r1 q2 q5 q3 q1 q6 q7 q4 r5 d1 r6 r3 r4 r2 r8 r7 d2 d3 d4 ?v ee i t1 i t2 02916-e-056 figure 56. simplified input stage
ad8065/ad8066 rev. g | page 21 of 28 layout, grounding, and by passing considerations power supply bypassing power supply pins are actually inputs and care must be taken so that a noise-free stable dc voltage is applied. the purpose of bypass capacitors is to create low impedances from the supply to ground at all frequencies, thereby shunting or filtering most of the noise. decoupling schemes are designed to minimize the bypassing impedance at all frequencies with a parallel combination of capacitors. 0.1 f (x7r or npo) chip capacitors are critical and should be as close as possible to the amplifier package. the 4.7 f tantalum capacitor is less critical for high frequency bypassing, and, in most cases, only one is needed per board at the supply inputs. grounding a ground plane layer is important in densely packed pc boards to spread the current minimizing parasitic inductances. however, an understanding of where the current flows in a circuit is critical to implementing effective high speed circuit design. the length of the current path is directly proportional to the magnitude of parasitic inductances and, therefore, the high frequency impedance of the path. high speed currents in an inductive ground return create unwanted voltage noise. the length of the high frequency bypass capacitor leads is most critical. a parasitic inductance in the bypass grounding works against the low impedance created by the bypass capacitor. place the ground leads of the bypass capacitors at the same physical location. because load currents flow from the supplies as well, the ground for the load impedance should be at the same physical location as the bypass capacitor grounds. for the larger value capacitors, which are effective at lower frequencies, the current return path distance is less critical.
ad8065/ad8066 rev. g | page 22 of 28 leakage currents poor pc board layout, contaminants, and the board insulator material can create leakage currents that are much larger than the input bias current of the ad8065/ad8066. any voltage differential between the inputs and nearby runs sets up leakage currents through the pc board insulator, for example, 1 v/100 g = 10 pa. similarly, any contaminants on the board can create significant leakage (skin oils are a common problem). to significantly reduce leakage, put a guard ring (shield) around the inputs and input leads that are driven to the same voltage potential as the inputs. this way there is no voltage potential between the inputs and surrounding area to set up any leakage currents. for the guard ring to be completely effective, it must be driven by a relatively low impedance source and should completely surround the input leads on all sides, above and below, using a multilayer board. another effect that can cause leakage currents is the charge absorption of the insulator material itself. minimizing the amount of material between the input leads and the guard ring helps to reduce the absorption. also, low absorption materials, such as teflon? or ceramic, could be necessary in some instances. input capacitance along with bypassing and ground, high speed amplifiers can be sensitive to parasitic capacitance between the inputs and ground. a few pf of capacitance reduces the input impedance at high frequencies, in turn increasing the amplifiers gain, causing peaking of the frequency response or even oscillations, if severe enough. it is recommended that the external passive components connected to the input pins be placed as close as possible to the inputs to avoid parasitic capacitance. the ground and power planes must be kept at a small distance from the input pins on all layers of the board. output capacitance to a lesser extent, parasitic capacitances on the output can cause peaking and ringing of the frequency response. there are two methods to effectively minimize their effect: ? as shown in figure 57 , put a small value resistor (r s ) in series with the output to isolate the load capacitor from the amps output stage. a good value to choose is 20 (see figure 10 ). ? increase the phase margin with higher noise gains or add a pole with a parallel resistor and capacitor from ?in to the output. r s = 20 v i ad8065 c l v o 02916-e-057 figure 57. output isolation resistor r sh = 10 11 v o r f c f c m r f c m c d c f +c s c s v b i photo 02916-e-058 figure 58. wideband photodiode preamp
ad8065/ad8066 rev. g | page 23 of 28 input-to-output coupling to minimize capacitive coupling between the inputs and output, the output signal traces should not be parallel with the inputs. wideband photodiode preamp figure 58 shows an i/v converter with an electrical model of a photodiode. the basic transfer function is ff f photo out rsc ri v + = 1 where i photo is the output current of the photodiode, and the parallel combination of r f and c f sets the signal bandwidth. the stable bandwidth attainable with this preamp is a function of r f , the gain bandwidth product of the amplifier, and the total capacitance at the amplifiers summing junction, including c s and the amplifier input capacitance. r f and the total capacitance produce a pole in the amplifiers loop transmission that can result in peaking and instability. adding c f creates a 0 in the loop transmission that compensates for the poles effect and reduces the signal bandwidth. it can be shown that the signal bandwidth resulting in a 45 phase margin (f (45) ) is defined by () s f cr cr f f = 2 45 where f cr is the amplifier crossover frequency, r f is the feedback resistor, and c s is the total capacitance at the amplifier summing junction (amplifier + photodiode + board parasitics). the value of c f that produces f (45) can be shown to be crf s f fr c c = 2 the frequency response in this case shows about 2 db of peaking and 15% overshoot. doubling c f and cutting the bandwidth in half results in a flat frequency response with about 5% transient overshoot. the preamps output noise over frequency is shown in figure 59 . frequency (hz) voltage noise (nv/ hz) 2 r f c f 2 r f (c f +c s +c m +2c d ) (c s +c m +2c d +c f )/c f r f noise ven (c f +c s +c m + 2c d )/c f f 3 f 2 f 3 = ven f 1 f 2 = f 1 = 1 1 f cr noise due to amplifier 02916-e-059 figure 59. photodiode voltage noise contributions the pole in the loop transmission translates to a 0 in the amplifiers noise gain, leading to an amplification of the input voltage noise over frequency. the loop transmission 0 introduced by c f limits the amplification. the noise gain bandwidth extends past the preamp signal bandwidth and is eventually rolled off by the decreasing loop gain of the amplifier. keeping the input terminal impedances matched is recommended to eliminate common-mode noise peaking effects, which adds to the output noise. integrating the square of the output voltage noise spectral density over frequency and then taking the square root allows users to obtain the total rms output noise of the preamp. table 5 summarizes approximations for the amplifier and feedback and source resistances. noise components for an example preamp with r f = 50 k, c s = 15 pf, and c f = 2 pf (bandwidth of about 1.6 mhz) are also listed. table 5. rms noise contributions of photodiode preamp contributor expression rms noise with r f = 50 k, c s = 15 pf, c s = 15 pf r f (2) 571 42 .frkt 2 f 64.5 v amp to f 1 1 fven 2.4 v amp (f 2 C f 1 ) 12 f dfm s ff c cccc ven ? +++ 2 31 v amp to (past f 2 ) 57.1 2 +++ 3 f fdm s f c cccc ven 260 v 270 v ( total )
ad8065/ad8066 rev. g | page 24 of 28 v cc v ee 1 / 2 ad8066 4.7 f 0.1 f r s1 4.7 f 0.1 f v n 2.2pf 500 r2 v p 1 / 2 ad8066 4.7 f 0.1 f 4.7 f 0.1 f ad8065 4.7 f 0.1 f 4.7 f 0.1 f v o r g v cc v ee v cc v ee 500 r4 r s2 500 r1 500 r3 r f = 500 2.2pf r f = 500 02916-e-060 figure 60. high speed instrumentation amplifier high speed jfet input instrumentation amplifier figure 60 shows an example of a high speed instrumentation amplifier with high input impedance using the ad8065/ad8066. the dc transfer function is () ? ? ? ? ? ? + ?= g pn out r vvv 10001 for g = +1, it is recommended that the feedback resistors for the two preamps be set to a low value (for instance 50 for 50 source impedance). the bandwidth for g = +1 is 50 mhz. for higher gains, the bandwidth is set by the preamp, equaling ( ) ( ) f gcr 3db rrf inamp = ? 2 / common-mode rejection of the in-amp will be primarily determined by the match of the resistor ratios r1:r2 to r3:r4. it can be estimated () () 211 21 ?+ ? = cm o v v the summing junction impedance for the preamps is equal to r f || 0.5(r g ). this is the value to be used for matching purposes. video buffer the output current capability and speed of the ad8065 make it useful as a video buffer, shown in figure 61 . the g = +2 configuration compensates for the voltage division of the signal due to the signal termination. this buffer maintains 0.1 db flatness for signals up to 7 mhz, from low amplitudes up to 2 v p-p (see figure 7 ). differential gain and phase have been measured to be 0.02% and 0.028, respectively, at 5 v supplies. +v s ?v s 4.7 f 0.1 f 2.2pf 499 249 75 499 v i ad8065 4.7 f 0.1 f 75 v o + ? + ? 02916-e-061 figure 61. video buffer
ad8065/ad8066 rev. g | page 25 of 28 outline dimensions 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarit y 0.10 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-012aa figure 62. 8-lead standard small outline package [soic] narrow body (r-8) dimensions shown in millimeters and (inches) pin 1 1.60 bsc 2.80 bsc 1.90 bsc 0.95 bsc 5 12 3 4 0.22 0.08 10 5 0 0.50 0.30 0.15 max seating plane 1.45 max 1.30 1.15 0.90 2.90 bsc 0.60 0.45 0.30 compliant to jedec standards mo-178-aa figure 63. 5-lead small outline transistor package [sot-23] (rt-5) dimensions shown in millimeters compliant to jedec standards mo-187-aa 0.80 0.60 0.40 8 0 4 8 1 5 pin 1 0.65 bsc seating plane 0.38 0.22 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.08 3.20 3.00 2.80 5.15 4.90 4.65 0.15 0.00 0.95 0.85 0.75 figure 64. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters
ad8065/ad8066 rev. g | page 26 of 28 ordering guide model temperature range package description package option branding ad8065ar ?40c to +85c 8-lead soic r-8 ad8065ar-reel ?40c to +85c 8-lead soic r-8 ad8065ar-reel7 ?40c to +85c 8-lead soic r-8 AD8065ARZ 1 ?40c to +85c 8-lead soic r-8 AD8065ARZ-reel 1 ?40c to +85c 8-lead soic r-8 AD8065ARZ-reel7 1 ?40c to +85c 8-lead soic r-8 ad8065art-reel ?40c to +85c 5-lead sot-23 rt-5 hra ad8065art-r2 ?40c to +85c 5-lead sot-23 rt-5 hra ad8065art-reel7 ?40c to +85c 5-lead sot-23 rt-5 hra ad8065artz-r2 2 ?40c to +85c 5-lead sot-23 rt-5 hra # ad8065artz-reel 2 ?40c to +85c 5-lead sot-23 rt-5 hra # ad8065artz-reel7 2 ?40c to +85c 5-lead sot-23 rt-5 hra # ad8066ar ?40c to +85c 8-lead soic r-8 ad8066ar-reel ?40c to +85c 8-lead soic r-8 ad8066ar-reel7 ?40c to +85c 8-lead soic r-8 ad8066arz 1 ?40c to +85c 8-lead soic r-8 ad8066arz-rl 1 ?40c to +85c 8-lead soic r-8 ad8066arz-r7 1 ?40c to +85c 8-lead soic r-8 ad8066arm ?40c to +85c 8-lead msop rm-8 h1b ad8066arm-reel ?40c to +85c 8-lead msop rm-8 h1b ad8066arm-reel7 ?40c to +85c 8-lead msop rm-8 h1b ad8066armz 1 ?40c to +85c 8-lead msop rm-8 h7c ad8066armz-reel7 1 ?40c to +85c 8-lead msop rm-8 h7c 1 z = pb-free part. 2 z = pb-free part, # denotes lead-free product, may be top or bottom marked.
ad8065/ad8066 rev. g | page 27 of 28 notes
ad8065/ad8066 rev. g | page 28 of 28 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c02916-0-1/06(g)

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